Optical-coherence-tomography (OCT) is a powerful technique with a wide range of applications, from imaging live tissue to non-destructive industrial testing. Coherent light sources for OCT in the short wave infra-red (SWIR) wavelength can achieve much higher resolution with wider bandwidth and penetration in opaque living tissue, such as brain and lung tissues. However, there is a lack of SWIR sources with the combined intensity and bandwidth to further enhance the OCT performance. The continued development of affordable and compact coherent light sources in this spectral range is important in many areas of modern technology. The combination of different semiconducting materials and light source architectures offers new paths for highly efficient SWIR sources at reduced cost. The central thrust of this research is to investigate the design of Ge based coherent light sources, with heterogeneous integration of InGaAs/Ge/InGaAs quantum-well structures on GaAs and large area, cost-effective Si substrates. Our objective is to develop tunable SWIR light sources capable of significantly higher penetration depth, image contrast and resolution than available from existing light sources, that will benefit a wide range of important medical, industrial and consumer applications.

To demonstrate the viability of the proposed approach, several key technical and scientific challenges must be addressed, including: (i) design and numerical simulation of the proposed strained 𝜀-Ge-based QW device architectures; (ii) materials synthesis and analysis of InGa(Al)As/ 𝜀-Ge/InGa(Al)As QW heterostructures using III-V strain template for modified bandgap of Ge; (iii) fabrication and demonstration of 𝜀-Ge QW coherent light sources in wavelength ranges from 1.7 µm to 2.5 µm; (iv) high carrier lifetime in tunable strained Ge; (v) implementation of an integration scheme of various materials on a substrate. To address (ii), (iii), (iv) and (v), the proposed research will utilize the state-of-the-art in-house epitaxial growth (interconnected group-IV and III-V molecular beam epitaxy chambers), collaborative materials characterization and simulation, and in-house/partner fabrication facilities. To address (i), a combination of numerical simulations and electronic structure theory will be leveraged to develop experimentally-calibrated InGaAs/𝜀-Ge/InGaAs QW device models necessary for broadband light emission in SWIR range. By investigating these topics, this research will elucidate numerous as-of-yet unexplored avenues of fundamental research, including: (a) the amount of strain and doping density in Ge to optical gain and emission wavelength; (b) the role of Ge layer thickness as a function of strain to optical gain; (c) the reduction of current density arising from non-radiative recombination; (d) the threshold current density with amount of strain in Ge; and (e) the realization of device-quality epitaxial Ge QW heterostructures on Si through minimization of dislocations and anti-phase domains in in-situ III-V buffer architectures on Si.

[1] M. K. Hudait et al. Design, Theoretical, and Experimental Investigation of Tensile-Strained Germanium Quantum-Well Laser Structure. ACS Appl. Electron. Mater. 2021, T10, 4535-4547.

[2] M. B. Clavel et al. Mapping the Interfacial Electronic Structure of Strain-Engineered Epitaxial Germanium Grown on In_xAl_1-xAs Stressors. ACS Omega, 2021.

[3] D. Saladukha et al. Direct and indirect band gaps in Ge under biaxial tensile strain investigated by photoluminescence and photoreflectance studies. Phys. Rev. B 2018, 97, 195304.

[4] M. Clavel et al. Heterogeneously-Grown Tunable Tensile Strained Germanium on Silicon for Photonic Devices. ACS Appl. Mater. Interfaces 2015, 7, 26470.

Current InAsSb and HgCdTe-based mid- and long-wavelength infrared (LWIR) detector systems are cryogenically cooled to suppress thermally-generated detector noise and maximize detector sensitivity, thereby limiting their maximum operating temperature. Additionally, these low bandgap materials present two key challenges for system integrators: (i) the lack of a lattice-matched substrate for defect-free photodetector (PD) materials growth; and (ii) the required low E_g PDs materials prohibit the fabrication of analog/digital readout circuitry from the same material. As such, the heterogeneous integration of tunable Sn compositional GeSn materials onto lattice matched III-V buffer would resolve the lattice-mismatch issue, enhance carrier lifetime, and open new avenues for the monolithic integration of detection and signal processing systems if integrated onto Si. The research focus is to: (i) develop device-quality, epitaxial, and tunable Sn compositional GeSn materials (0-20% Sn) integrated on lattice-matched InAl(Ga)As buffers via dual-chamber MBE growth system; and (ii) demonstrate PDs with flexible (via lifting off from substrate) and tunable-wavelength via different Sn composition into GeSn during material synthesis. Intelligent buffer design will promote defect-free, device-quality GeSn epitaxy, allowing device designers to leverage the following benefits by adopting GeSn: (i) a direct bandgap Ge-based material; (ii) high carrier lifetime; (iii) lattice-matched epitaxy (no thickness constraints); and (iii) a tunable detector cutoff wavelength. By taking a holistic approach to innovating at the materials and devices level, the resulting GeSn materials will be analyzed via several methods to qualify/quantify the materials synthesis for subsequent demonstration of GeSn -based long wavelength PDs.

Tunable LWIR detectors based on InAsSb materials on GaSb promises efficiencies greater than 50% (see, Infrared detectors by A. Rogalski, 2nd ed., page 342), it will be remarkable if these efficiencies can be translated onto a GaAs substrate, especially in > 10 µm wavelength regime. However, there are many fundamental challenges that arise while attempting to monolithically integrate these n-InAsSb/B-InAlSb/n-InAsSb n-B-n detectors onto GaAs substrate. First and foremost, there is a challenge in realizing device-quality InAsSb material on GaAs itself due to lattice mismatch. Second, there needs to be a breakthrough in the implementation of low defect density buffer that will bridge the lattice constant of active region of detector (n-InAsSb/B-InAlSb/n-InAsSb) and the GaAs substrate. Third challenge is to control the Sb composition and atomic intermixing at each heterointerface of active region. Last one is to achieve precise band alignment of n-InAsSb absorber/B-InAlSb barrier/n-InAsSb contact layer heterointerfaces for detectors with low dark current and enhanced figure-of-merits. This involves materials-driven research into the design, synthesis, characterization and development of > 10 µm long-wavelength infrared n-B-n detectors on GaAs substrate via metamorphic buffer through understanding the electronic band structure and interface manipulation of InAs_1-ySb_y/In_xAl_1-xSb hetero-engineered n-B-n heterostructure materials.

[1] M. K. Hudait et al. Carrier Lifetimes in Epitaxial Ge_1-ySn_y/Al(Ga)As Heterostructures with Variable Tin Composition. J. Materials Chemistry C 2022, 10, 10530-10540.

[2] M. K. Hudait et al. Structural, Morphological and Magnetotransport Properties of Composite Semiconducting and Semimetallic InAs/GaSb Superlattice Structure. Materials Advances 2020, 1, 1099-1112.

This research focuses on materials synthesis procedures, metal-oxide-semiconductor device fabrication process flows, and materials and device characterization techniques centered on the low bandgap group IV semiconductor Ge and ternary compound semiconductor InGaAs. By exploiting epitaxial strain, improved carrier mobility and a tunable device threshold voltage were realized, thus enabling low-power computing devices for the next generation of microprocessor and integrated circuit (IC) technologies. Such low-power ICs will function at operating frequencies and voltages where the current Si-based IC technology cannot, thereby enabling new markets within the embedded and ubiquitous computing (Internet-of-Things) fields. Moreover, leveraging the same Ge and InGaAs materials, future photonic and optoelectronic devices can be monolithically integrated with logic (computing) functionality, thereby enabling lower-cost distributed and personal computing utilizing larger and faster data transfer rates. Together, these findings help pave the way towards energy-efficient computing devices that require lower power to operate, can be integrated with next-generation photonic and optoelectronic platforms, and enable usage models untapped by current microprocessor and IC technology. This research is the first of its kind to comprehensively investigate and outline the feasibility of Ge- and InGaAs-based materials and electronic devices for the next generation of computing devices. As such, the results have a wide range of applications, from computing to communication technologies. The preliminary simulation and experimental results found in this work suggest that Ge- and InGaAs-based electronics are capable of operating under conditions that state-of-the-art Si-based electronics cannot.

[1] J. -S. Liu et al. TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low Voltage IoT Applications. IEEE J. Electron Dev. Soc. 2019, 7, 210.

[2] J. -S. Liu et al. Performance Evaluation of Novel Strain Engineered Ge-InGaAs Heterojunction Tunnel Field Effect Transistors. IEEE Trans. Electron Dev. 2015, 62, 3223.

[3] M. Clavel et al. Strain-Engineered Biaxial Tensile Epitaxial Germanium for High-Performance Ge/InGaAs Tunnel Field-Effect Transistors. IEEE J. Electron Devices Soc. 2015, 3, 184.

Using ADSEL's experience and expertise in material/device fabrication as well as device physics modeling, a cohesive approach to establishing novel IV and III-V based CMOS logic devices is pursued. Germanium is gaining popularity in photonic and optoelectronic devices. Whereas III-V based devices have already gained popularity in optical applications. The ability to integrate fast and power efficient Ge and III-V based logic devices alongside Ge and III-V based optical devices would be a significant step closer to an integrated optoelectronic chip for future applications in photonics and quantum computing. This research focusses on developing a reliable CMOS structure from device physics modeling to demonstration of proof of concept.

The Si CMOS feature size scaling faces several challenges, including: (i) minimization of leakage current (IOFF); (ii) maintaining high drive current (ION) necessary for circuit fan-out and high-speed operation; and (iii) supply voltage (VDD) scaling to reduce total power dissipation and increase performance per watt without degrading (i) and (ii). New channel materials with narrow bandgaps and higher carrier mobilities than Si show great promise for continued technology scaling. Moreover, these new materials would benefit from leveraging existing Si process infrastructure in order to be commercially feasible alternatives to Si CMOS. One major drawback associated with using III-V based channels for making logic devices is the electron-hole mobility mismatch between complementary devices. It is possible to make very-high mobility electron devices which can form excellent n-channel devices, but it is often difficult to get the same mobility for holes in order to make equivalent p-channel devices. The search for novel materials and device architectures to replace existing Silicon based transistors requires a consideration of the trade-off between performance and feasibility. New channel material, InGaAs and strained Ge (𝜀-Ge) with narrow bandgaps and higher carrier mobilities than Si, show great promise at low voltage operation and promise for continued technology scaling, predicted by our recent modeling work. To address this challenge, device modeling (using classical and quantum numerical analysis), materials synthesis (advanced dual chamber MBE at ADSEL), material and interface characterization (X-ray, AFM, TEM, Raman Spectroscopy, Hall mobility and Ellipsometry) and process optimization of monolithically co-integrated InGaAs and Ge on Si is proposed. Our approach is the most innovative and transformative of all monolithically co-integrated epitaxial layers which allows us to precise control the Ge fin height, InGaAs composition and fin height, interfacial defect density, in-house device modeling and materials growth and analysis, device processing, testing, and benchmarking, for achieving alternate channel low power high speed logic on Si.

[1] S. K. Saluru et al. Performance Analysis of TaSiOx Inspired sub-10nm Energy Efficient InGaAs Quantum Well Tri-gate Technology. IEEE J. Electron Dev. Soc. 2017, 5, 496.

[2] P. Nguyen et al. Investigating FinFET Sidewall Passivation Using Epitaxial (100)Ge and (110)Ge Metal-Oxide-Semiconductor Devices on AlAs/GaAs. IEEE Trans. Electron Dev. 2017, 64, 4457.

Heterointerfaces of two materials (e.g., InGaAs/InAlAs, InAsSb/InAlSb) can impart unprecedented transport that can be exploited in tailoring electronic and optoelectronic functions on silicon (Si) substrate. Researchers have been aggressively investigating of such heterostructures, and the holy grail remains the heterogeneous integration of materials that are best for individual functionalities, such as light emission, modulation, and detection. There have been studies on addressing integration issues such as, large lattice mismatch and thermal expansion differences between active layer of interest and the Si; however, there is no common buffer platform for integration of electronic and photonic functions. To address these challenges, novel and radical changes in metamorphic buffer architecture and device design are essential, where one can integrate both electronic and photonic device structure on the same buffer layer.

This research work involves materials-driven research "to develop novel tunable lattice constant buffer platform on Si " for transistors, laser, and detectors.

[1] M. K. Hudait (Invited). Heterogeneously Integrated III-V on Silicon for Future Nanoelectronics. ECS Transactions 2012, 45, 581.

[2] M. Radosavljevic et al. Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications. IEDM 2009, 319-322.