Shuvodip Bhattacharya
Email: shuvob1[at]vt[dot]edu
Education:
M. S. ,Electrical and Electronics Engineering, Texas A&M University, College Station, December 2016
B.S., Electrical and Communication Engineering, Heritage Institute of Technology, Kolkata, May 2014
MS Thesis Title:
"A study of ozone as an oxygen source for the growth of high-κ dielectric films for gate dielectric on GaN/AlGaN/GaN"
Research:
Shuvodip is interested in the fabrication and study of Ge-based FinFET devices on Si using wide-bandgap III-V buffer for the development of post-Si CMOS era.
Hobbies: Shuvodip enjoys music, playing guitar, calligraphy, photography, traveling and reading.

Rutwik Joshi
Email: rutwikj[at]vt[dot]edu
Education:
M. Tech. ,Microelectronics(RFDT), Indian Institute of Technology, Delhi 2019
B.Tech., Electronics Engineering, VIT Pune, 2017
MS Thesis Title:
"Physical and Analytical Modelling of Non-linearity in CMOS compatible Co-planar waveguide using Sentaurus TCAD"
Research:
Rutwik is interested in exploring novel device architectures and materials for future applications in optoelectronics and quantum electronics.
Hobbies: Rutwik enjoys astrophysics, philosophy, hiking and jogging.

Sengunthar Karthikeyan
Email: karthikms91[at]vt[dot]edu
Education:
M. Tech. , Indian Institute of Technology (Indian School of Mines) Dhanbad, May 2019.
B.Tech., Birla Vishwakarma Mahavidyalaya (Gujarat Technological University-GTU, Gujarat), June 2013.
M. Tech. Thesis Title:
"The Understanding of 5.25 GHz, 39 dB Cascode Low Noise Amplifier using Tunnel Field Effect Transistor"
Research:
Karthik is interested in exploring Group IV based materials (Ge, GeSn) and their heterostructures on Group III-V buffer for optoelectronics.
Hobbies: Karthik enjoys reading, traveling, hiking and jogging.

Michael Clavel
Email: mbclavel[at]vt[dot]edu
Education:
Ph. D. , Electrical Engineering, Virginia Tech, December 2023
M. S., Virginia Tech, December 2015
B.S., Electrical Engineering, Virginia Polytechnic Institute and State University, 2013
MS Thesis Title:
"Tensile-Strained Ge/InxGa1-xAs Heterostructures for Electronic and Photonic Applications"
PhD Thesis Title:
"Tensile-Strained Ge/III-V Heterostructures for Low-Power Nanoelectronic Devices"

Michael is working at Booz Allen Hamilton.

Jheng-Sin Liu
Email: jsliu[at]vt[dot]edu
Education:
Ph. D. , Electrical Engineering, Virginia Tech, December 2017
M. S.,Graduate Institute of Photonics and Optoelectronics,National Taiwan University,Taiwan, 2013
B.S., Electrical Engineering, National Tsing Hua University,Taiwan,2011
MS Thesis Title:
"Three-dimensional Simulation on N-type Wafer-based Solar Cells"
PhD Thesis Title:
"Advanced Energy-Efficient Devices for Ultra-Low Voltage System: Materials-to-Circuits"

Jheng is working at Intel Corporation, Portland, OR as a Senior Process Engineer.

Aheli Ghosh
Email: gaheli3[at]vt[dot]edu
Education:
M. S. , Electrical Engineering, Virginia Tech, May 2017
B.E., Instrumentation and Electronics Engineering, Jadavpur University, Kolkata, 2015
MS Thesis Title:
"Heteroepitaxial Germanium-on-Silicon Thin-Films for Electronic and Photovoltaic Applications"

Aheli is currently pursuing towards her PhD degree @ GIT.

Sarat Saluru
Email: sarks93[at]vt[dot]edu
Education:
M. S. , Electical Engineering, Virginia Tech, May 2017
B. E., Electronics and Communication Engineering, People's Education Society University, Bangalore, 2015
MS Thesis Title:
"Projection of TaSiOx/In0.53Ga0.47As Tri-gate transistor performance for future Low-Power Electronic Applications"

Sarat is working at Northrop Grumman, Baltimore, MD as a Research Engineer.

Peter D. Nguyen
Email: petern[at]vt[dot]edu
Education:
M. S. , Electrical Engieering, Virginia Tech, May 2016
B.S., Electrical Engineering, Virginia Polytechnic Institute and State University, 2014
MS Thesis Title:
"Heteroepitaxial Ge on Si via High-Bandgap III-V Buffers for Low-Power Electronic Applications"

Peter is working at Intel Corporation, Portland, OR as a Process Engineer.

Patrick Goley
Email: patrick[dot]goley[at]vt[dot]edu
Education:
M. S. , Electrical Engieering, Virginia Tech, July 2015
B.S., Electrical Engineering, Virginia Polytechnic Institute and State University, 2013
MS Thesis Title:
"Plastic Relaxation of Highly Tensile Strained (100) Ge/InGaAs Heterostructures"

Patrick is currently working towards his PhD degree @ Georgia Tech.

Nikhil Jain
Email: jain34[at]vt[dot]edu
Education:
Ph. D. , Electrical Engineering, Virginia Tech, March 2015
M. S., Electrical Engineering, Virginia Tech, May 2013
B.S., University of Illinois at Urbana Champaign, 2010
MS Thesis title:
"Design of III-V multijunction solar cells on Si substrate"
PhD Thesis Title:
"Heterogeneous Integration of III-V Multijunction Solar Cells on Si Substrate: Cell Design & Modeling, Epitaxial Growth & Fabrication"

Nikhil is currently working as a Device Engineer at Alta Devices, Livermore, CA.

Yan Zhu
Email: zhuyan[at]vt[dot]edu
Education:
Ph. D. , Electrical Engineering, Virginia Tech, April 2014
M.E., Institute of Semiconductors, Chinese Academy of Sciences, China, 2011
B.S., School of Physics, Shandong University, China, 2008
PhD Thesis Title:
"Mixed As/Sb and tensile strained Ge/InGaAs heterostructures for low-power tunnel field effect transistors (TFETs)"

Yan is currently working as Staff Scientist at Lumentum, Livermore, CA.

Siddharth Vijayaraghavan
Email: svijayar[at]vt[dot]edu
Education:
M. Engineering , Virginia Tech, 2012
M.S., University of Houston, 2009
B.E., Anna University, 2006
Project Report:
MBE lab set up, literature review, mask design and TEM sample preparation and imaging.

Siddharth is currently working for AMD, Austin, Texas.

Bipin Dhavale
Email: bipinpd[at]vt[dot]edu
Education:
M. Engineering , Virginia Tech, 2011
B.E., Visvesvaraya Technological University, 2003



Bipin is currently working for Altera Corporation, San Jose, California.

Will Banner
Email: will6[at]vt[dot]edu
Education:
B. S. , Electrical Engineering, Virginia Tech, May 2020
B. S. , Physics, Virginia Tech, May 2020
UG Research:
Interface characterization of PE-ALD and ALD deposited high-K dielectrics on epitaxial (100) and (110)InGaAs MOS-Cs.

Will is currently working towards his PhD degree @ MIT.

Patrick Goley
Email: patrick[dot]goley[at]vt[dot]edu
Education:
B. S. , Virginia Tech, 2013
UG Honors Thesis:
Electrical Characterization of Oxide-Semiconductor Interfaces.

Patrick is currently working towards his M. S. degree @ADSEL, Virginia Tech. Received NSF Graduate Research Fellowship 2013.

Peter Nguyen
Email: petern[at]vt[dot]edu
Education:
B. S. , Virginia Tech, 2014
UG Research:
Interface characterization of high-K dielectrics on InGaAs and Si MOS-C.


Peter is currently working towards his M. S. degree @ADSEL, Virginia Tech. Received NSF Graduate Research Fellowship 2014.

Krishna Neupane
Email: krishna1[at]vt[dot]edu
Education:
B. S. , Electrical Engineering, Virginia Polytechnic Institute and State University, 2013



Currently working at United States Patent and Trademark Office.

Yingying Gui
Email: gyingy3[at]vt[dot]edu
Education:
B. S. , Electrical Engineering, Virginia Polytechnic Institute and State University, 2016
Research:
Yingying is interested in Evaluating Mixed Arsenide/Antimonide MOS Interfaces for Low-Power Electronics.
Hobbies: Yingying enjoys travelling.

Yingying is currently working towards his M. S. degree at Virginia Tech.

Usman Maqsood
Email:
Education:
B. S. , Virginia Tech, 2011
Summer Research:
Contact formation on III-V materials using Physical Vapor Deposition (PVD).

Currently working as a Power Electronics Design Engineer at Boeing, Saint Peters, Missouri.